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 Preliminary Datasheet TLE 6215 G
Smart Two Channel Low-Side Switch
Features * Power limitation * Overtemperature protection * Overload protection * Short circuit protection * Diagnostic feedback * Overvoltage protection * C compatible input * Electrostatic discharge (ESD) protection Product Summary Supply voltage Drain source voltage On resistance Output current Nom. output current VS VDS(AZ)max RON (typ) ID ID(ISO) 6.5 - 40 60 0.21 2x4 2 x 1.3 V V A A
Application * All kinds of resistive and inductive loads (relays,electromagnetic valves) * C compatible power switch * Solenoid control switch in automotive and industrial control systems P-DSO-24-3 General description Double channel Low-Side-Switch in Smart Power Technology (SPT) with two seperate inputs and two open drain DMOS output stages. The TLE 6215 G is fully protected by embedded protection functions and designed for automotive and industrial applications.
Block Diagram
VS Vbb Thermal overload
TLE 5224 G2 TLE 6215 G
Open Load Overload OU T1 Vbb Load 1
ENA
IN1 ST1
LOGIC
R PD
Open Load
Load 2
IN2 LOGIC
Overload OU T2
ST2
R PD
GND
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Block Diagram of Open Load Detection
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Maximum Ratings for Tj = - 40C to 150C
Parameter Supply voltage Supply voltage operational range Continuous drain source voltage (OUT1, OUT2) Input voltage IN1, IN2, ENA Status output voltage Operating temperature range Storage temperature range Output current per channel Output current at reversal supply Status output current Inductive load single switch off dissipation energy Tj = 25C C Electrostatic Discharge Voltage (HBM) according to MIL STD 883D, method 3015.7 and EOS/ESD assn. Standard S5.1 - 1993 Output 1,2 Pins All other Pins Thermal resistance Symbol VS VS VDS VIN VST Tj Tstg ID(lim) ID 1,2 IST EAS Values - 0.3 ... + 40 + 4.8 ... + 40 45 - 0.3 ... + 6 - 0.3 ... + 32 - 40 ... + 150 - 55 ... + 150 Overload shutdown -4 - 5 ... + 5 50 Unit V V V V V C A A mA mJ
VESD VESD
4000 2000 12 75 10000
V V K/W h
junction - case1 RthJC junction - ambient RthJA tb
Maximum operating lifetime (according to "Ambient thermal conditions")
Ambient thermal conditions
Pos 11 12 13 14 15 16 17 TAmbient temperature range -40 C -20 C 25 C 60 C 80 C 100 C > 120 C operating periods 2% 10 % 24 % 34 % 24 % 5% 1%
1
Case = Pin 5 to 8 and 17 to 20. Additionally the pins not connected (N.C.) have to be connected to the ground plane used as thermal heatsink to achieve the best thermal resistance.
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Pin Definitions and Functions
Pin 1 2 3 4 5,6,7,8 9,10 11 12 13,14,15,16 17,18,19,20 21 22 23 24 Symbol IN1 ST2 OUT2 N.C. GND N.C. ENA VS N.C. GND N.C. OUT1 ST1 IN2 Function Control input channel 1 Status output channel 2 Power output channel 2 Not connected, cooling Ground, cooling Not connected, cooling Enable input for both channels Supply voltage Not connected, cooling Ground, cooling Not connected, cooling Power output channel 1 Status output channel 1 Control input channel 2
Pin Configuration(top view)
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Electrical Characteristics
Parameter and Conditions VS = 6.5 to 40 V ; Tj = - 40 C to + 150 C (unless otherwise specified) 1. Power Supply (VS) Supply current (Outputs ON) Supply current (Output OFF) Operating voltage 2. Power Outputs ON state resistance; ID = 4A; VS 9.5 V Z-Diode clamping voltage (OUT1, OUT2) Pull down resistor Output on delay time 2 Output off delay time 2 Output on fall time 2 Output off rise time 2 Output off status delay time 2 Output on status delay time 2 3 4 Overload switch-off delay time 3 3. Digital Inputs (IN1, IN2, ENA) Input low voltage Input high voltage Input voltage hysteresis Input pull down current Enable pull down current VINL VINH VINHys VIN =5 V; VS 9 V IIN VENA =5 V; VS 9 V IENA - 0.3 2.0 0.2 50 15 100 30 1.0 6.0 0.6 140 45 V V V A A Tj = 25 C Tj = 150C RDS(ON) VDS(AZ) Tj = 25 C RPD Tj 125 C ID = 0.2 A ID = 2 A ID = 0.2 A ID = 2 A ID = 2 A ton toff tfall trise t4 t5 tDSO 45 14 10 10 20 25 40 20 25 40 0.21 0.42 60 26 40 40 V k s VS = 40 V VS 18 V VS 18 V IS 2,5 IS VS 4.8 1,5 5 4 3 40 mA mA V Symbol Values min Unit typ max
20 50
60 50 150
4. Digital Status Outputs (ST1, ST2), open Drain Output voltage low Leakage current high IST = 2 mA VSTL ISTH 0.5 10 V A
See timing diagram, resitive load condition; VS 9 V This parameter will not be tested but assured by design 4 Time till status valid after switching on or error detection
2 3
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Electrical Characteristics
Parameter and Conditions VS = 6.5 to 40 V ; Tj = - 40 C to + 150 C (unless otherwise specified) 5. Diagnostic Functions Open load detection voltage (Output OFF) Open load compare voltage Overload threshold current Overtemperature shutoff threshold 6 Hysteresis
5
Symbol
Values min
Unit typ max
VS 18 V VS = 12 V 18V > VDSC > 0.65*VS VS 9.5 V
VDS(OL) VDS(OL)C ID(OL) ID(lim) Tth Thys
0.515*VS
0.585*VS
V V mA A
6.2 VDSC-1.6 100 5 170 10
7.0 VDSC-0.9 500
Open load detection current (Output ON)
200
C K
Application Description
This IC is specially designed to drive inductive loads (relays, electromagnetic valves). Integrated clamp-diodes limit the output voltage peak when switching off an inductive load. For the detection of errors there are two status outputs, which monitor the following errors by logic levels: - thermal overload, - open and short load to ground in active an inactive mode, - overloading of output (also shorted load to supply) in active mode.
Circuit Description
Input Circuits The control and enable inputs, all active high, consist of Schmitt triggers with hysteresis. All inputs are connected with pull-down current sources. Not connected inputs are interpreted as "low". Switching Stages The power outputs consist of a DMOS power transistor with open drain. The output stages are shortload-protected throughout the operating range. Integrated clamp-diodes limit voltage spikes produced when inductive loads are discharged. Protective Circuit The outputs are protected against current overload. There is no protection against reverse polarity of the supply voltage.
5 6
VDSC is the output voltage of the other channel used for open load compare detection This parameter will not be tested but assured by design
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Error Detection The status output signal of the switching stages at normal operation is LOW = OFF; HIGH = ON. In case of any error the status outputs are set according to the table below. If current overload or thermal overload occurs, the error condition is stored in an internal register and the output is shutdown. To reset this register the control input of the affected channel has to be switched off and then on again. The state of the error detection circuit is directly dependent on the input status. Open load is detected for both on- and off-modus. In the on-modus the load current is monitored. If it drops below the specified threshold open load is detected. In the off mode, the ouput voltage is monitored. An open load condition is detected when the output voltage of a given channel is below 55 % of the supply voltage V Also the output voltages of two outputs are compaired against each other in off S. condition with a fixed offset of typ. 1.25 V to recognize GND bypasses. To suppress fault diagnosis during the flyback phase of the compared output, the diagnostic circuit includes a latch function. Reset of this latch is done at end of the flyback phase, additionally it can be reseted by a low signal on the enable input and by a high signal of the input signal. See also the block diagramm of open load detection.
Diagnostic Table
Operating Condition ENA L H H H H X L H X L H X L H L H H L H H Inputs IN1 X L H L H L X H L H H 1) X L H 1) IN2 X L L H H L X H 1) L H H 1) X L H
Power Outputs Status Outputs
OUT1 OFF OFF ON OFF ON OFF OFF OFF OFF OFF ON 1) OFF OFF OFF 1)
OUT2 OFF OFF OFF ON ON OFF OFF OFF 1) OFF OFF ON 1) OFF OFF OFF
ST1 L L H L H L L L H H L 1) L L L 1)
ST2 L L L H H L L L 1) H H L 1) L L L
Normal Function
Thermal Overload
Open Load Channel 1
Open Load Channel 2
Overload Channel 1
Overload Channel 2
1) see normal function
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Test Circuit
Application Circuit
The blocking capacitor C is recommended to avoid critical negative voltage spikes on VS in case of battery interruption during OFF-commutation.
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Timing Diagram
VIN VI NH VINL t VDS
VS 90%
t on
t off
10%
t t fall t rise
VST
t5
t4
t
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Package and ordering code
all dimensions in mm
P - DSO - 24 - L16
Ordering code
(Dual-in-line package, small-outline) 24 B 24 DIN 41870 T17
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
0.36 +0 .13
1.27
0.76 ma x
15.4-0.2
2.45 -0.2 0.1 min
7.6 -0.2
2.65 max
+0 .07
0.25
10.3
0.3
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Published by Infineon Technologies AG, Bereichs Kommunikation St.-Martin-Strasse 76, D-81541 Munchen (c) Infineon Technologies AG 1999 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that lifesupport device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
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Revision List:
19.06.2001 30.11.2001 01.03.2002 28.04.2002
Target Datasheet First revision Second revision Preliminary Datasheet
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